This chapter describes the Clock Management Units (CMUs) of Exynos 4412 SCP. CMUs control Phase Locked Loops (PLLs) and generate system clocks for CPU, buses, and function clocks for inpidual IPs in Exynos 4412 SCP. They also communicate with the power management unit (PMU) in order to stop clocks before entering certain low power mode to reduce power consumption by minimizing clock toggling.

本章节描述了Exynos4412片上系统的时钟管理单元（CMUs）。CMUs控制锁相环（PLLs）产生系统时钟，供CPU、总线和Exynos4412片上系统的个别设备端口（IPs）来使用。当进入低电压模式前需要停止时钟以小化时钟切换带来的电源损耗的时候，时钟管理单元（CMUs）会同电源管理单元（PMU）交互。

 

7.1 Clock Domains。时钟域

In Exynos 4412 SCP, it clocks the function blocks asynchronously with each other to provide a wider choice of operating frequencies. It also eases physical implementation.

在Exynos4412片上系统中，它为各个功能块之间的异步通信提供一个宽泛的操作频率区间。它还能消除各个功能块的时钟物理硬件的实现。

 

1） CPU block consists of the Cortex-A9 MPCore processor, L2 cache controller, and CoreSight. It operates at voltage levels of 0.875 V ~ 1.30 V. The Cortex-A9 MPCore operates at 200 MHz ~ 1.4 GHz and CoreSight Clock is up to 200MHz. The CMU in CPU block (CMU_CPU) generates all the necessary clocks for IPs in CPU block. It also generates certain control signals for Cortex-A9 MPCore.

CPU块由Cortex-A9多核处理器、L2缓存控制器和CoreSight跟踪架构。工作电压区间为 0.875 V ~ 1.30 V。 Cortex-A9的工作频率区间为200 MHz ~ 1.4 GHz。CoreSight 时钟的上限值为200MHZ。在CPU区中的时钟管理单元 (CMU_CPU)生成在CPU块中所有设备端口所需的时钟频率。Cortex_A9核心的频率也是由它产生的。

 

2） DMC block consists of the DRAM memory controller (DMC), Security sub-system (SSS), and Generic Interrupt Controller (GIC). CMU in DMC block (CMU_DMC) generates 400 MHz DRAM clock, 200 MHz AXI bus clock which is synchronized with the DRAM clock, and 100MHz clock for register accesses. It also generates 200 MHz clock for Accelerator Coherency Port (ACP) bus, which is used for memory coherency checking and connects CPU and SSS bus masters.

DMC块由DRAM存储控制器（DMC）、安全子系统（SSS）和通用中断控制器（GIC）组成。CMU在DMC块（CMU_DMC）产生400MHZ的DRAM时钟、200MHZ的用作同步DRAM的AXI总线时钟 和 100MHZ的寄存器通道时钟。它还为用来内存相干性检查、连接cpu或安全子系统总线主控制器的总线，叫加速干预端口(ACP)总线，产生一个200MHZ的时钟。

 

3）The LEFTBUS and RIGHTBUS blocks contain the global data buses that are clocked at 200 MHz. The global data buses transfer data between the DRAM and various sub-blocks. It also contains global peripheral buses that are clocked at 100 MHz. You can use 100 MHz clock for register accesses.

LEFTBUS和RIGHTBUS子块包含一个时钟为200MHZ的全局数据总线。全局数据总线在DRAM和各个子块之间传输数据。它同样包含时钟为100MHZ的全局外围总线。可以使用100MHZ的时钟频率在寄存器通道上。

 

4）CMU_TOP generates clocks for all the remaining function blocks, which include G3D, MFC, LCD0, ISP, CAM, TV, FSYS, MFC, GPS, MAUDIO, PERIL, and PERIR. It generates bus clocks that operate at 400 / 200 / 160 / 133 / 100 MHz. It also generates various special clocks to operate IPs in Exynos 4412 SCP. 

CMU_TOP为所有剩下的子块产生时钟。剩下的子块包括： G3D, MFC, LCD0, ISP, CAM, TV, FSYS, MFC, GPS, MAUDIO, PERIL, 和 PERIR。它产生总线时钟工作在400/ 200/ 160/ 133/ 100MHZ。它同样可以用来为Exynos4412的片上系统端口产生特殊的时钟。

 

5）Additionally asynchronous bus bridges are inserted between two different function blocks.

还有，在不同的功能块之间有一个异步总线桥。

       

7.2 Clock Declaration时钟描述

The top-level clocks in Exynos 4412 SCP are:

> Clocks from clock pads, namely, XRTCXTI, XXTI, and XUSBXTI.

> Clocks from CMUs

For instance, ARMCLK, ACLK, HCLK, and SCLK

@ ARMCLK specifies clock for Cortex-A9 MPCore (up to 800 MHz @1.0 V, 1 GHz @ 1.1 V).

@ ACLK, HCLK, PCLK specify bus clocks.

@ SCLK (Special clock) specifies all clocks except bus clocks and processor core clock.

>Clocks from USB PHY

>Clocks from HDMI_PHY

>Clocks from GPIO pads

 

在Exynos4412片上系统中的顶层级别的时钟都有：

1）来自时钟垫的时钟，如：XRTCXTI, XXTI, and XUSBXTI.

2）来自CMUs的时钟：如，ARMCLK, ACLK, HCLK, and SCLK

@ ARMCLK规定了Cortex-A9多核处理器的时钟；

@ ARMCLK, ACLK, HCLK, 和SCLK规定了总线时钟；

@SCLK(特殊时钟)规定了除了总线时钟和处理器核心时钟外的所有时钟。

3）来自USB PHY的时钟

4）来自HDMI_PHY的时钟

5）来自GPIO根的时钟

 

 

7.2.1 Clocks from Clock Pads

The clock pads derive the clocks. They are:

时钟垫是时钟的来源。他们是：

1) XRTCXTI: Specifies the clock generated from the crystal pad of 32.768 KHz with XRTCXTI and XRTCXTO pins. XRTCXTI and XRTCXTO are the two pins of crystal pad. RTC uses this clock as a source to the real-time clock. It requires a parallel resistance of 10 MΩ between the XUSBXTI and XUSBXTO pins.

1）XRTCXTI：说明了时钟来自有 XRTCXTI 和 XRTCXTO管脚的32.768KHZ的水晶垫。 XRTCXTI 和 XRTCXTO是水晶垫的两个管脚。RTC使用这样的时钟作为实时时间的时钟。这需要在 XRTCXTI 和 XRTCXTO管脚之间安置平行 10 MΩ阻抗。

 

2) XXTI: Specifies the clock from external oscillator with XXTI pins. XXTI use wide-range OSC pads. When USB PHY is not used in commercial set, CMUs and phase-locked loops, namely, APLL, MPLL, VPLL, and EPLL use this clock as a supply source for appropriate modules. The input frequency of the clock ranges from 12 MHz to 50 MHz. When XXTI pin is not used, the pin should be tied to ground (GND). You can use the XXTI pin only for testing purpose.

2）XXTI：表明时钟来自有XXTI引脚的外部震荡器。XXTI使用宽范围的OSC源。当USB PHY不使用商业模块套件时，CMUs和锁相环（又叫APLL,MPLL,和VPLL）使用这种时钟来支持恰当的模块。时钟的输入频率为12MHZ到50MHZ之间。当XXTI管脚闲置不用是，应该接地。你只能使用XXTI管脚作为测试一用。

 

3) XUSBXTI: Specifies the clock from crystal pad with XUSBXTI and XUSBXTO pins. XUSBXTI and XUSBXTO use wide-range OSC pads. This clock is supplied to the USB PHY and the phase locked loops, namely, APLL, MPLL, VPLL, and EPLL. Refer to Chapter 36 USB HOST and Chapter 37 USB DEVICE, for more information. We recommend using a 24 MHz crystal as the iROM design is based on the 24 MHz input clock. It requires parallel resistance of 5MΩbetween the XUSBXTI and XUSBXTO pins.

3）XUSBXTI：表明时钟来自接有XUSBXTI和XUSBXTO管脚的时钟垫。XUSBXTI和XUSBXTO使用宽范围的OSC源。这种时钟支持USB PHY和锁相环（又叫APLL/MPLL/VPLL和EPLL）。详情请参考36章USB HOST和37章节USB DEVICE。我们推荐使用24MHZ水晶来设计iROM是建立在有24MHZ的输入时钟的基础上的。它需要在 XUSBXTI和XUSBXTO管脚之间使用一个5MΩ的水平阻抗。

 

7.2.2 Clocks from CMU 来自CMU的时钟

CMUs generate internal clocks with intermediate frequencies using from clocks from the clock pads. They are:

CMUs使用来自时钟垫的时钟，产生中等频率的内部时钟。使用的时钟垫有：

1）Clock pads, namely, XRTCXTI, XXTI, and XUSBXTI

2）Four PLLs, namely, APLL, MPLL, EPLL, and VPLL

3）USB PHY and HDMI PHY

 

Some of these clocks are selected, pre-scaled, and provided to the corresponding modules. We recommend using 24 MHz input clock source for APLL, MPLL, EPLL, and VPLL. The components to generate internal clocks are:

其中有个时钟被选中，接着预分频，然后提供给通信模块通信。我们推荐使用24MHZ提供给APLL/MPLL/EPLL/VPLL锁相环作为输入时钟源。生成内部时钟的组件有：

1）APLL uses FINPLL as input to generate frequencies from 22 to 1400 MHz.

2）MPLL uses FINPLL as input to generate frequencies from 22 to 1400 MHz.

3）EPLL uses FINPLL as input to generate frequencies from 22 to 1400 MHz. This PLL generates a 192 MHz clock for the Audio Sub-system. It pides EPLL output to generate 24 MHz SLIMbus clock.

4）VPLL uses FINPLL or SCLK_HDMI24M as input to generate frequencies from 22 to 1400 MHz. This PLL generates 54 MHz video clock or G3D clock.

5）USB Device PHY uses XUSBXTI to generate frequencies of 30 and 48 MHz.

6）HDMI PHY uses XUSBXTI to generate 54 MHz.

 

In typical Exynos 4412 SCP applications,

1）Cortex-A9 MPCore, CoreSight, and HPM use APLL.

2）DRAM, system bus clocks, and other peripheral clocks like audio IPs, and SPI use MPLL and EPLL.

3）Video clock uses VPLL.

4）G3D uses MPLL or VPLL as input clock source.

Clock controllers allow bypassing of PLLs for low frequency clock. They also provide clock gating to each block, thereby reducing power consumption.

在典型的Exynos 4412片上系统的应用中，

1）Cortex-A9多核处理器核心、CoreSight 和 HPM 使用 APLL.

2）DRAM、系统总线时钟和其他的外围时钟（如 audio设备端口）和SPI使用MPLL和EPLL

3）视频时钟使用VPLL

4）G3D使用MPLL 或者 VPLL作为输入时钟源。

时钟控制器允许使用PLLs来支持降频，同时也支持为每个设备块提供倍频，以此来减轻电源消耗。

 

 

7.3 Clock Relationship

The clock relationship between various clocks are:

各个时钟之间的关系有：

1） CPU_BLK clocks

@ freq (ARMCLK) = freq (MOUTCORE)/n, where n = 1 to 16

@ freq (ACLK_COREM0) = freq (ARMCLK)/n, where n = 1 to 8

@ freq (ACLK_COREM1) = freq (ARMCLK)/n, where n = 1 to 8

@ freq (PERIPHCLK)  = freq (ARMCLK)/n, where n = 1 to 8

@ freq (ATCLK)  = freq (MOUTCORE)/n, where n = 1 to 8

@ freq (PCLK_DBG)  = freq (ATCLK)/n, where n = 1 to 8

 

2） DMC_BLK clocks

@ freq (SCLK_DMC)  = freq (MOUTDMC_BUS)/n, where n = 1 to 8

@ freq (ACLK_DMCD)  = freq (SCLK_DMC)/n, where n = 1 to 8

@ freq (ACLK_DMCP)  = freq (ACLK_DMCD)/n, where n = 1 to 8

@ freq (ACLK_ACP)  = freq (MOUTDMC_BUS)/n, where n = 1 to 8

@ freq (PCLK_ACP)  = freq (ACLK_ACP)/n, where n = 1 to 8

@ freq (SCLK_C2C)  = freq (MOUTC2C)/n, where n = 1 to 8

@ freq (ACLK_C2C)  = freq (SCLK_C2C)/n, where n = 1 to 8

3）LEFTBUS_BLK clocks

@ freq (ACLK_GDL)  = freq (MOUTGDL)/n, where n = 1 to 8

@ freq (ACLK_GPL)  = freq (ACLK_GDL)/n, where n = 1 to 8

4）RIGHTBUS_BLK clocks

@ freq (ACLK_GDR)  = freq (MOUTGDR)/n, where n = 1 to 8

@ freq (ACLK_GPR)  = freq (ACLK_GDR)/n, where n = 1 to 8

5）CMU_TOP clocks

@ freq (ACLK_400_MCUISP  = freq (MOUTACLK_400_mcuisp)/n, where n = 1 to 8

@ freq (ACLK_200)  = freq (MOUTACLK_200)/n, where n = 1 to 8

@ freq (ACLK_100)  = freq (MOUTACLK_100)/n, where n = 1 to 16

@ freq (ACLK_160)  = freq (MOUTACLK_160)/n, where n = 1 to 8

@ freq (ACLK_133)  = freq (MOUTACLK_133)/n, where n = 1 to 8

@ freq (SCLK_ONENAND)  = freq (MOUTONENAND)/n, where n = 1 to 8

6）MAUDIO_BLK clocks

@ freq (RP_CLK) = freq (MOUTASS)/n, where n = 1 to 16

@ freq (BUS_CLK)  = freq (MOUTRP)/n, where n = 1 to 16

 

Caution:  Ensure that the ratio between the SCLK_DMC and ACLK_DMCD frequency should be 2:1 or 1:1

always. Do not change this ratio during the running state of DMC. You should also ensure that the

ratio between the SCLK_C2C and ACLK_C2C frequency should be 2:1. You should not change this

ratio during the running state of C2C.

警告：确保SCLK_DMC:ACLK_DMCD = 2:1或者1:1；不能在DMC运行状态的时候改变这个比率。同时应该确保SCLK_C2C：ACLK_C2C = 2:1；不能在C2C运行状态是改变该值。

 

The values for high-performance operation are:

高性能操作使用值如下：

 

•  freq (ARMCLK)  = 1400 MHz at 1.3 V

•  freq (ACLK_COREM0)  = 350 MHz at 1.3V

•  freq (ACLK_COREM1)  = 188 MHz at 1.3 V

•  freq (PERIPHCLK) = 1400 MHz at 1.3 V

•  freq (ATCLK)  = 214 MHz at 1.3 V

•  freq (PCLK_DBG) = 107 MHz at 1.3 V

•  freq (SCLK_DMC) = 400 MHz at 1.0 V

•  freq (ACLK_DMCD) = 200 MHz at 1.0 V

•  freq (ACLK_DMCP) = 100 MHz at 1.0 V

•  freq (ACLK_ACP)  = 200 MHz at 1.0 V

•  freq (PCLK_ACP)  = 100 MHz at 1.0 V

•  freq (SCLK_C2C)  = 400 MHz at 1.0 V

•  freq (ACLK_C2C)  = 200 MHz at 1.0 V

•  freq (ACLK_GDL)  = 200 MHz at 1.0 V

•  freq (ACLK_GPL)  = 100 MHz at 1.0 V

•  freq (ACLK_GDR) = 200 MHz at 1.0 V

•  freq (ACLK_GPR) = 100 MHz at 1.0 V

•  freq (ACLK_400_MCUISP) = 400 MHz at 1.0 V

•  freq (ACLK_200)  = 160 MHz at 1.0 V

•  freq (ACLK_100)  = 100 MHz at 1.0 V

•  freq (ACLK_160)  = 160 MHz at 1.0 V

•  freq (ACLK_133)  = 133 MHz at 1.0 V

•  freq (SCLK_ONENAND)  = 160 MHz at 1.0 V

 

The PLL operations are:

1） APLL mainly drives the CPU_BLK clocks. It generates frequencies up to 1.4 GHz with a duty ratio of 49:51.

APLL also generates DMC_BLK, LEFTBUS_BLK, RIGHTBUS_BLK, and CMU_TOP clocks as supplement of

MPLL.

2）MPLL mainly drives the DMC_BLK, LEFTBUS_BLK, RIGHTBUS_BLK, and CMU_TOP clocks. It generates

frequencies up to 1 GHz with a duty ratio of 49:51. MPLL also generates CPU_BLK clocks when it blocks

APLL for locking during the Dynamic Voltage Frequency Scaling (DVFS).

3）EPLL mainly generates an audio clock.

4）VPLL mainly generates video system operating clock of 54 MHz, or a G3D clock, or 440 MHz clock at 1.1 V.

 

锁相环的用法：

1）APLL主要用来驱动CPU_BLK时钟。当占空比为49:51时，能产生一个高频率1.4GHZ。APLL也能产生DMC_BLK/ LEFTBUS_BLK/ RIGHTBUS/ CMU_TOP时钟，用来给MPLL提供驱动支持。

2）MPLL主要驱动DMC_BLK/ LEFTBUS_BLK/ RIGHTBUS_BLK/ CMU_TOP时钟。占空比为49:51时，MPLL能产生一个高频率1GHZ。当MPLL用来阻塞APLL在动态电压扫描（DVFS）时的锁定时，MPLL也产生CPU_BLK时钟。

3）EPLL主要用来产生一个音频时钟。

4）VPLL主要用来产生一个54MHZ的视频系统操作时钟，或者一个G3D时钟，或者一个在1.1V电压下的440MHZ时钟。

 

 

 

7.3.3 Recommended PLL PMS Value for VPLL

Table 7-4 describes the recommended PLL PMS value for VPLL. 

表7-4描述了推荐的VPLL对应的PLL计划维护体系值。

NOTE: 

1.  Although there is an equation for choosing PMS values, we strongly recommend only the values in the above table.

If you have to use other values, please contact us.

2.  K value description "Positive value (Negative value)": Positive values is that you should write to EPLLCON/VPLLCON register. Negative value is that you can calculate PLL output frequency with it.

注意：

1. 尽管有选择PMS值的计算方程等式。但是我们强烈推荐仅使用以上表格中的值。如果你必须使用表格以外的值，请联系三星公司。

2. K 值描述了正负值：正值要写到EPLLCON或者VPLLCON寄存器。负值你可以用它来乘以PLL的输出值。

 

 

7.4 Clock Generation时钟的产生

Figure 7-2 and Figure 7-3, illustrates the block diagram of the clock generation logic. The clock generator consists of an external crystal clock that is connected to the oscillation amplifier. The PLL converts the incoming low frequency to a high frequency clock that is required by the Exynos 4412 SCP. The clock generator also includes a built-in logic to stabilize the clock frequency for each system reset. The clock requires a specified time for stabilization.

图7-2和图7-3，插图说明了时钟产生逻辑的区域表。时钟发生器由一个连接到震荡放大器上的外部晶振组成。锁相环PLL把接收到的低频转化为Exynos4412片上系统所需的高频。时钟生成器同样也需要一个内嵌的逻辑单元来为每次重置系统建立稳定的时钟频率。时钟需要一段特定的时间来稳定下来。

 

Figure 7-2 and Figure 7-3 illustrates the two types of clock MUX. Clock MUX in grey color represents glitch-free clock MUX that is free of glitches while changing the clock selection. Clock MUX in white color represents non- glitch-free clock MUX that can suffer from glitches while changing the clock sources. You have to be careful while using each clock MUX.

图7-2和图7-3，插图说明了两种类型的时钟复用器(MUX)。灰色的时钟复用器表示一种无干扰的时钟复用器，也就是在改变时钟选区时不受干扰。白色的时钟复用器表示有干扰的时钟复用器，也就是说在改变时钟源时，要遭受脉冲信号。要小心使用任何一个时钟复用器。

 

For glitch-free MUX, you should ensure that all clock sources are running while changing the clock selection. If not, it implies that the clock selection process is not complete and it results in clock output having unknown states. The clock MUX status registers are identified with a keyword that starts with CLK_MUX_STAT

对于无干扰性的复用器，你需要在改变时钟选区时确保每一个时钟源都在工作。如果不能保证，这就表明了选择时钟的过程并没有完成，会导致未知的时钟输出状态。时钟复用器的状态计算器被认定为CLK_MUX_STAT开始。

For non-glitch-free clock MUX, glitches may occur while changing the clock selection. To prevent glitch signals, we recommend disabling the output of a non-glitch-free MUX before any change of clock selection. After completing the clock change, you can re-enable the output of the non-glitch-free clock MUX. This is done to ensure that there are no glitches resulting due to the clock change selection. The outputs of non-glitch-free MUXES are masked by the clock source mask control registers. The clock source mask control registers are identified with a keyword that starts with CLK_SRC_MASK.

对于有干扰性时钟复用器，在改变时钟选区的时候可能有脉冲信号的产生。为了避免有脉冲信号的影响，我们建议在时钟选区改好之前，先关闭这种复用器的输出功能。在完成选区的更换后，你可以重新使能复用的输出功能。有干扰型的时钟复用器的输出功能"MUXES"在时钟源屏蔽控制寄存器中可被屏蔽。时钟源屏蔽控制寄存器以“CLK_SRC_MASK”关键字开头标识。

 

Figure 7-2 and Figure 7-3 illustrates a clock pider that indicates possible piding value in parentheses. The piding values can be changed by clock pider registers during run-time. Some clock piders have only one piding value and you are not allowed to change the piding value.

图7-2和图7-3，插图说明了一个时钟分频器，可以从其输入源来对时钟分频。在运行态，分频值可以通过修改时钟分频寄存器来修改。但是有一些时钟分频器只有一种分频值，其分频值不允许被修改。

 

Figure 7-2 illustrates the Exynos 4412 SCP Clock Generation Circuit (CPU, BUS, DRAM, and ISP Clocks) diagram.

图7-2插图说明了Exynos4412片上系统时钟生成电路（CPU/BUS/DRAM/ ISP时钟）表。

 

Figure 7-3 illustrates the Exynos 4412 SCP Clock Generation Circuit (Special Clocks) diagram.

图7-3插图说明了Exynos4412片上系统的时钟生成电路（特殊时钟）表